1) Field of the Invention
The present invention relates to a metal-oxide semiconductor (MOS) field-effect transistor in which distortion is applied to one of semiconductor layers in a heterojunction structure that is formed with two different types of semiconductor layers having different lattice constants, and a manufacturing method thereof.
2) Description of the Related Art
Conventionally, improvement in performance of MOS field-effect transistors has been achieved through microstructuring. In recent years, MOS field-effect transistors of higher performance that are capable of high-speed operation with low leakage current are demanded for high-speed processing in information processing and data communication, and for low power consumption. However, the microstructuring of the MOS field-effect transistors in accordance with the conventional scaling law are approaching the limit thereof.
As one method of achieving high-speed operation, it has been known that distortion is introduced to channels to change the properties of a material of the channels, thereby improving electron mobility.
For example, in techniques disclosed in Japanese Patent Application Laid-open Nos. H9-321307 and 2001-332745, silicon (Si) is laminated on a relaxed silicon-germanium (SiGe) layer, and large distortion is added thereto. Thus, electron mobility is greatly improved, thereby drastically improving properties of nMOS field-effect transistors.
Moreover, in a technique disclosed in Japanese Patent Application Laid-open No. 2002-93921, a stress is generated in a gate electrode to apply to a channel region of a silicon substrate. Thus, channel properties of MOS field-effect transistors are improved without using the distorted silicon substrate.
However, with any of the conventional techniques, it is difficult to achieve improvement both in terms of manufacturing costs and of properties of high-speed operation and low power consumption.
In view of the above problems, it is an object of the present invention to provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons and holes are drastically improved, thereby realizing high-speed operation and low power consumption.
Furthermore, it is an object of the present invention to provide a MOS field-effect transistor that is advantageous in terms of costs by this manufacturing method of a MOS field-effect transistor, maintaining high consistency with existing processes without drastically changing the processes.